Suppose an instruction loads a value that is not in the closest data cache. The CPU must obtain the relevant cache line before dependent instructions can use the value. The details of lookup order, speculation, and coherence depend on the processor.
1. Translate and check
The load begins with a virtual address. Address translation uses a translation lookaside buffer (TLB) when possible; a TLB miss may require a page-table walk. The resulting physical address is compared with cache tags to see whether the line is present at the relevant cache level.
2. Search lower levels
On a miss, the request proceeds through lower cache levels and possibly to the memory controller. If another core owns a modified copy, a coherence protocol may obtain data from that cache instead of DRAM. “Cache miss means RAM access” is therefore an oversimplification.
3. Fill a line
The system transfers a block of neighboring bytes and allocates it in one or more caches according to policy. The requested word becomes available, and the waiting instruction can complete. Independent instructions may continue executing while the load waits, but dependent work cannot use the missing value.
4. Reuse nearby data
Later accesses to the same line can be faster while it remains cached. Sequential scans often benefit from fetching adjacent bytes together. A pointer chain has weaker spatial locality and must often wait for one load before discovering the next address.
This model explains patterns, not fixed latency numbers. Measure on the target machine and use counters or a simulator such as the CS:APP Cache Lab to study the access pattern.