A strong answer
A load checks the relevant cache levels after address translation. If the requested line is missing, the processor requests it from a lower level or memory system. Instructions that depend on the loaded value cannot complete until it arrives, but independent instructions may execute meanwhile if the processor can find useful work and resources are available.
Out-of-order execution and speculation can hide some latency; they cannot make an unknown dependent address available early. A pointer chain often has this dependency: each load reveals the address of the next. A sequential scan exposes predictable neighboring addresses and can use cache-line data efficiently.
The requested line may come from a lower cache or a coherent copy in another core, not necessarily directly from DRAM. Exact lookup order, line size, replacement, and latency depend on the processor. I would use hardware counters or a controlled benchmark to test a claim on the target machine.
Follow-up direction
Describe spatial and temporal locality, then explain why replacing a branch with extra memory operations is not automatically an optimization.